1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, more specifically, a nonvolatile semiconductor memory device having a cross-point type memory cell array in which a plurality of two-terminal memory cells each having a nonvolatile variable resistance elements are arranged in the form of a matrix in a row direction and a column direction, one terminals of memory cells belonging to the same row are connected to the same row selecting line, and the other terminals of memory cells belonging to the same column are connected to the same column selecting line.
2. Description of the Related Art
In recent years, a cross-point type semiconductor memory device (to be arbitrarily referred to as a “cross-point memory” hereinafter) in which memory cells do not include selective elements except for memory elements, and memory elements are directly connected to a column selecting line (to be referred to as a “data line” hereinafter) and a row selecting line (to be referred to as a “bit line” hereinafter) to form a memory cell array.
In the cross-point memory, since the memory cell array can be simplified and advantageous to integration but does not include a selecting transistor for each memory cell, control of a leakage current generated in reading and programming is a very important problem as described in Japanese Unexamined Patent Publication No. 2006-155846.
In this case, the leakage current means a leak current generated depending on a resistance distribution in a memory cell array through a non-selected memory cell. A cause of generation of a leakage current will be briefly described below with reference to a memory cell array 90 shown in FIG. 17.
In order to perform reading from a selected memory cell M11, for example, a voltage Vread (selected bit line voltage) is applied to a bit line B1 connected to a selected memory cell, a voltage Vbias (non-selected bit line voltage) is applied to bit lines B2 and B3 connected to a non-selected memory cell, and the voltage Vbias is applied to data lines D1 to D3. A voltage Vread-Vbias is applied across two terminals of a selected memory cell, and an amount of current flowing in the data line (selected data line) D1 connected to the selected memory cell is read by a sense amplifier. However, a current (current path IA in FIG. 17) flowing in the selected data line D1 is a sum of a current flowing in the selected memory cell M11 and a current flowing in half-selected memory cells M21 and M31 connected to the selected data line D1 and connected to the non-selected bit lines B2 and B3, respectively. A non-selected memory cell connected to a bit line and a data line one of which is selected and the other of which is non-selected will be called a “half-selected memory cell” hereinafter.
Since the voltage Vbias is applied to a selected data line and a non-selected bit line, no current flows in a memory cell connected to the selected data line and the non-selected bit line in principle. However, since a voltage on a selected data line side of the selected memory cell is divided by a resistance of a driver which drives the data line and a resistance of the selected memory cell (furthermore, a resistance of a driver which drives the bit line), the voltage actually varies from Vbias depending on a resistance state stored in the selected memory cell. Similarly, a potential of the non-selected bit line also varies depending on a resistance state stored in the memory cell.
In this manner, since a potential difference is generated between the selected data line and the non-selected bit line, a leakage current flowing from the selected data line D1 to the non-selected bit lines B2 and B3 through the half-selected memory cells M21 and M31 or from the non-selected bit lines B2 and B3 to the selected data line D1 through the half-selected memory cells M21 and M31 is generated. Furthermore, when the potential difference is generated between the non-selected data line and the non-selected bit line, a current flowing from the non-selected bit line to the non-selected data line or from the non-selected data line to the non-selected bit line is generated. For this reason, for example, when a current flowing from a non-selected data line D2 to the non-selected bit line B2 is generated, the current flows from the non-selected data line D2 to the selected data line D1 through a non-selected memory cell M22, a non-selected bit line B2, and the half-selected memory cell M21 (current path IB in FIG. 17) to cause an increase in leakage current. The increase in leakage current through the non-selected bit line and the non-selected data line is an outstanding problem because the number of non-selected lines increases when an array size becomes large.
As a conventional technique of the leakage current control, a circuit configuration of a voltage suppressing circuit described in Japanese Unexamined Patent Publication No. 2006-155846 is shown in FIG. 18.
A voltage suppressing circuit 91 in FIG. 18 has one terminal connected to a data line or a bit line of a memory cell array 90 and the other terminal connected to a voltage supply circuit. An ON resistance of a transistor 92 is controlled by an output from an inverter 93, and an output from the inverter 93 is controlled by a signal level of a data line or a bit line. Therefore, a voltage supplied to the data line or the bit line is adjusted by an inversion level of the inverter 93 and a threshold voltage of the transistor 92.
However, when the voltage suppressing circuit 91 tries to solve the problem of a leakage current, the voltage suppressing circuit naturally detects a variation in voltage and then adjusts a voltage, leakage (to be referred to as “initial leakage” hereinafter) occurs in a short period from when the voltage varies to when the voltage is adjusted.
This will be described with reference to an example in FIG. 18, the gate of the transistor 92 is not opened or closed until the inverter 93 detects a variation in voltage of the data line or the bit line. Since the transistor 92 does not operate until the voltage of the data line or the bit line actually departs from a default value, a moment in which an unexpected initial leakage current flows is necessarily present independently of the capability of the inverter 93 or the transistor 92.
A resistive random access memory is expected to be practically used as a high-speed memory having a large capacitance and a speed of several nanoseconds, and so the initial leakage is an unignorable problem in an array size or an operation speed at a practical-use level.